Pulse 280 Spezifikationen PDF herunterladen (Seite 12)

Operational Description of HRPWM

www.ti.com

2.3 Principle of Operation

The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific

data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that

time steps are optimally applied and that edge placement accuracy is maintained over a wide range of

PWM frequencies, system clock frequencies and other operating conditions. Table 3 shows the typical

range of operating frequencies supported by the HRPWM.

Table 3. Relationship Between MEP Steps, PWM Frequency and Resolution

System MEP Steps Per PWM MIN PWM MAX Res. @ MAX

(MHz) SYSCLKOUT

(1) (2) (3)

(Hz)

(4)

(MHz) (Bits)

(5)

50.0 111 763 2.50 11.1

60.0 93 916 3.00 10.9

70.0 79 1068 3.50 10.6

80.0 69 1221 4.00 10.4

90.0 62 1373 4.50 10.3

100.0 56 1526 5.00 10.1

(1)

System frequency = SYSCLKOUT, i.e., CPU clock. TBCLK =SYSCLKOUT.

(2)

Table data based on a MEP time resolution of 180 ps (this is an example value, see the device-specific data sheet for MEP

limits.

(3)

MEP steps applied = T

SYSCLKOUT

/180 ps in this example.

(4)

PWM minimum frequency is based on a maximum period value, i.e., TBPRD = 65535. PWM mode is asymmetrical up-count.

(5)

Resolution in bits is given for the maximum PWM frequency stated.

High-Resolution Pulse Width Modulator (HRPWM) SPRU924F– April 2005– Revised October 2011

Submit Documentation Feedback

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 41 42

Keine Kommentare

Pulse 280 Spezifikationen Seite 12