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2.7.2 Controlling and Monitoring the Trip-Zone Submodule

2.7.3 Operational Highlights for the Trip-Zone Submodule

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Trip-Zone (TZ) Submodule

The trip-zone submodule operation is controlled and monitored through the following registers:

Table 2-17. Trip-Zone Submodule Registers

(1)

TZSEL 0x0012 No Trip-Zone Select Register

reserved 0x0013

TZCTL 0x0014 No Trip-Zone Control Register

TZEINT 0x0015 No Trip-Zone Enable Interrupt Register

TZFLG 0x0016 No Trip-Zone Flag Register

TZCLR 0x0017 No Trip-Zone Clear Register

TZFRC 0x0018 No Trip-Zone Force Register

(1)

All trip-zone registers are EALLOW protected and can be modified only after executing the EALLOW instruction. For more

information, see the device-specific version of the System Control and Interrupts Reference Guide listed in Section 1.

The following sections describe the operational highlights and configuration options for the trip-zone

submodule.

The trip-zone signals at pins TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals.

When one of these pins goes low, it indicates that a trip event has occurred. Each ePWM module can be

individually configured to ignore or use each of the trip-zone pins. Which trip-zone pins are used by a

particular ePWM module is determined by the TZSEL register for that specific ePWM module. The

trip-zone signals may or may not be synchronized to the system clock (SYSCLKOUT) and digitally filtered

within the GPIO MUX block. A minimum 1 SYSCLKOUT low pulse on TZn inputs is sufficient to trigger a

fault condition in the ePWM module. The asynchronous trip makes sure that if clocks are missing for any

reason, the outputs can still be tripped by a valid event present on TZn inputs , providing the GPIO is

appropriately configured. For more information, see the GPIO section of the device-specific version of the

System Control and Interrupts Reference Guide listed in Section 1 .

Each TZn input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for a

ePWM module. The configuration is determined by the TZSEL[CBCn] and TZSEL[OSHTn] control bits

(where n corresponds to the trip pin) respectively.

• Cycle-by-Cycle (CBC):

When a cycle-by-cycle trip event occurs, the action specified in the TZCTL register is carried out

immediately on the EPWMxA and/or EPWMxB output. Table 2-18 lists the possible actions. In addition,

the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a EPWMx_TZINT interrupt is generated if it

is enabled in the TZEINT register and PIE peripheral.

The specified condition on the pins is automatically cleared when the ePWM time-base counter

reaches zero (TBCTR = 0x0000) if the trip event is no longer present. Therefore, in this mode, the trip

event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually

cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the

TZFLG[CBC] bit is cleared, then it will again be immediately set.

• One-Shot (OSHT):

When a one-shot trip event occurs, the action specified in the TZCTL register is carried out

immediately on the EPWMxA and/or EPWMxB output. Table 2-18 lists the possible actions. In addition,

the one-shot trip event flag (TZFLG[OST]) is set and a EPWMx_TZINT interrupt is generated if it is

enabled in the TZEINT register and PIE peripheral. The one-shot trip condition must be cleared

manually by writing to the TZCLR[OST] bit.

The action taken when a trip event occurs can be configured individually for each of the ePWM output

pins by way of the TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in

Table 2-18 , can be taken on a trip event.

SPRU791F – November 2004 – Revised July 2009 ePWM Submodules 61

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